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9337d-auto-07/14 features supply voltage up to 40v operating voltage v s = 5v to 28v supply current sleep mode: typically 9a silent mode: typically 47a very low current consumption at low supply voltages (2v < v s < 5.5v): typically 130a linear low-drop voltage regulator, 85ma current capability: mlc (multi-layer ceramic) capacitor with 0 esr normal, fail-safe, and silent mode atmel ata663254: v cc = 5.0v 2% atmel ata663231: v cc = 3.3v 2% sleep mode: vcc is switched off active mode atmel ata663203: v cc = 5.0v 2% vcc undervoltage detection with open drain re set output (nres, 4ms reset time) voltage regulator is short-circuit and over-temperature protected lin physical layer according to lin 2.0, 2.1, 2.2, 2.2a and saej2602-2 wake-up capability via lin bus (100s dominant) wake-up source recognition txd time-out timer bus pin is over-temperature and short-ci rcuit protected versus gnd and battery advanced emc and esd performance fulfills the oem ?hardware requirements for lin in automotive applications rev.1.3? interference and damage protection according to iso7637 qualified according to aec-q100 package: dfn8 with wettable flanks (moisture sensitivity level 1) note: 1. lin sbc: lin system basis chip including lin transceiver and voltage regulator. ata663203/ata663231/ata663254 lin bus device family incl uding voltage regulator and lin sbc (1) with compatible footprint datasheet
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 2 1. description the atmel ? ata6632xx device family includes two basic products; a lin system basis chip (sbc) and a low-drop voltage regulator with compatible footprints. the atmel ata663231/54 (system basis ch ip) is a fully integrat ed lin transceiver, design ed according to the lin specification 2.0, 2.1, 2.2, 2.2a and saej2602-2, with a lo w-drop voltage regulator (3.3v/5v/85ma). the combination of voltage regulator and bus transceiver makes it possible to develop simple but powerful slave nodes in lin bus systems. atmel ata663231/54 is designed to handle the low-speed data co mmunication in vehicles (f or example, in convenience electronics). improved slope control at th e lin driver ensures secure data communi cation up to 20kbaud. the bus output is designed to withstand high voltage. sleep mode and silent mode guarantee minimized current consumption even in the case of a floating or a sh ort-circuited lin bus. the atmel ata663203 (voltage regulator) is a fully integrated lo w-drop voltage regulator, with 5v output voltage and 85ma current capability. it is especially designe d for the automotive environment. a key f eature is that the current consumption is always below 170a (without load), even if the supply voltage is below the regulator ?s nominal output voltage. figure 1-1. block diagram lin transceiver with integrated voltage regulator (sbc) table 1-1. ata6632xx device family description atmel ata6632xx lin-sbc with 3.3v regulator 31 lin-sbc with 5v regulator 54 voltage regulator 5v 03 5 gnd 2 en 4 txd 1 rxd vcc 8 nres 3 short-circuit and overtemperature protection voltage regulator normal/silent/ fail-safe mode 3.3v/5v control unit normal and fail-safe mode rf-filter lin vs 7 6 txd time-out timer slew rate control undervoltage reset sleep mode vcc switched off wake-up bus timer atmel ata663231/54 receiver v cc - + v cc v cc
3 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 figure 1-2. block diagram voltage regulator pmos + - voltage reference undervoltage reset 7 8vcc 3 nres 5 vs gnd atmel ata663203
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 4 2. pin configuration figure 2-1. pinning dfn8 table 2-1. pin description pin symbol function 1 rxd receive data output 2 en enables normal mode if the input is high 3 nres vcc undervoltage output, open drain, low at reset 4 txd transmit data input 5 gnd ground, heat slug 6 lin lin bus line input/output 7 vs supply voltage 8 vcc output voltage regulator 3.3v/5v/85ma backside heat slug, internally connected to the gnd pin vcc nc vs gnd nc nres nc nc ata663203 dfn8 3 x 3 voltage regulator vcc lin vs gnd rxd nres en txd ata663231 ata663254 dfn8 3 x 3 sbc
5 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 3. pin description 3.1 supply pin (vs) lin operating voltage is v s = 5v to 28v. undervoltage detection is implemented to disable transmission if v s falls below typ. 4.5v, thereby avoiding false bus messages. after switching on v s , the ic starts in fail-safe mo de and the voltage regulator is switched on. the supply current in sleep mode is typically 9a and 47a in silent mode. 3.2 ground pin (gnd) the ic does not affect the lin bus in the ev ent of gnd disconnection. it is able to handle a ground shift of up to 11.5% of v s . 3.3 voltage regulator output pin (vcc) the internal 3.3v/5v voltage regulator is capable of driving lo ads up to 85ma, supplying the microcontroller and other ics on the pcb and is protected against overload by means of curr ent limitation and overtemperatur e shutdown. furthermore, the output voltage is monitored and causes a reset signal at the nres output pin if it drops below a defined threshold v vcc_th_uv_down . 3.4 undervoltage reset output (nres) if the v cc voltage falls below the undervoltage detection threshold v cc_th_uv_down , nres switches to low after t res_f . the nres stays low even if v cc = 0v because nres is internally driven from the v s voltage. if v s voltage ramps down, nres stays low until v s < 1.5v and then becomes highly impedant. the implemented undervoltage delay keeps nres low for t reset = 4ms after v cc reaches its nominal value. 3.5 bus pin (lin) (sbc only) a low-side driver with internal current lim itation and thermal shutdown as well as an internal pull-up resistor according to li n specification 2.x is implemented. the volt age range is from ?27v to +40v. this pin exhibits no reverse current from the lin bus to v s , even in the event of a gnd shift or v bat disconnection. the lin receiver thresholds comply with the lin protocol specification. the fall time (from recessive to dominant) and the rise time (from dominant to re cessive) are slope-controlled. during a short circuit at lin to v bat , the output limits t he output current to i bus_lim . due to the power dissipation, the chip temperature exceeds t linoff and the lin output is switched off. the ch ip cools down and after a hysteresis of t hys , switches the output on again. rxd stays on high because lin is high. the v cc regulator works independently during lin overtemperature switch-off. during a short circuit from lin to gnd the ic can be switched into sleep or silent mode and even in this case the current consumption is lower than 100a in sleep mode and lower than 120a in silent mode. if the short-circuit disappears, the ic starts with a remote wake-up. the reverse current is < 2a at pin lin during loss of v bat . this is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition.
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 6 3.6 input/output (txd) (sbc only) in normal mode the txd pin is the microcontroller interface for controlling the state of the lin output. txd must be pulled to ground in order to drive the lin bus low. if txd is high or un connected (internal pull-up resist or), the lin output transistor is turned off and the bus is in the recessive state. if the txd pi n stays at gnd level while switch ing into normal mode, it must be pulled to high level longer than 10s before the lin driver can be activated. this feature prevents the bus line from being accidentally driven to dominant state after normal mode has been activated (also in case of a short circuit at txd to gnd). during fail-safe mode, this pin is used as output and signals the fail-safe source. the txd input has an internal pull-up resistor. an internal timer prevents the bus line from being driven perm anently in the dominant state. if txd is forced to low longer than t dom > 20ms, the lin bus driver is switch ed to the recessive state. nevertheless, when switching to sleep mode, the actual level at the txd pin is relevant. to reactivate the lin bus driver , switch txd to high (> 10s). 3.7 output pin (rxd) (sbc only) in normal mode this pin reports the state of the lin bus to the microcontroller. lin high (recessive state) is indicated by a high level at rxd; lin low (dominant stat e) is indicated by a low level at rxd. the output is a push-pull stage switching between vcc and gnd. the ac characteristics are measured by an external load capacitor of 20pf. in silent mode the rxd output switches to high. 3.8 enable input pin (en) (sbc only) the enable input pin controls the operating mode of the device. if en is high, the circuit is in normal mode, with transmission paths from txd to lin and from lin to rxd both active. t he vcc voltage regulator operat es with 3.3v/5v/85ma output capability. if en is switched to low while txd is still high, the device is forced to silent mode. no data tr ansmission is then possible, a nd current consumption is reduced to i vssilent typ. 47a. the vcc regulator retains its full functionality. if en is switched to low while txd is low, the device is fo rced to sleep mode. no data transmission is possible, and the voltage regulator is switched off. the en pin provides a pull-down resistor to force the transceiver into recessive mode if en is disconnected.
7 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 4. functional description 4.1 physical layer compatibility because the lin physical layer is independent of higher lin layers (e.g., lin protoc ol layer), all nodes with a lin physical layer according to revision 2.x can be mixe d with lin physical layer nodes based on ea rlier versions (i.e., lin 1.0, lin 1.1, lin 1.2, lin 1.3) with out any restrictions. 4.2 operating modes figure 4-1. sbc operating modes table 4-1. sbc (ata663254, ata663231) operating modes operating mode transceiver v cc (sbc only) lin txd rxd fail-safe off 3.3v/5v recessive signaling fail-safe sources (see table 4-2 ) normal on 3.3v/5v txd-dependent follows data transmission silent (sbc only) off 3.3v/5v recessive high high sleep/unpowered off 0v recessive low low a: vs > v vs_th_u_f_up (2.4v) b: vs < v vs_th_u_down (1.9v) c: bus wake-up event (lin) e: vs < v vs_th_n_f_down (3.9v) f: vs > v vs_th_f_n_up (4.9v) d: vcc < v vcc_th_uv_down (2.4v/4.2v) en = 1 en = 0 go to sleep command go to silent command en = 0 txd = 0 bc & f en = 0 txd = 0 en = 0 txd = 1 en = 1 & f txd = 1 d, e b a b & f fail-safe mode vcc: on 5v/3.3v vcc monitor active communication: off wake-up signalling undervoltage signalling normal mode vcc: 5v/3.3v vcc monitor active communication: on sleep mode vcc: off communication: off unpowered mode all circuitry off silent mode vcc: 5v/3.3v vcc monitor active communication: off c & f, d en = 1 & f & f & d & f
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 8 figure 4-2. voltage regulator operating modes 4.2.1 normal mode (sbc only) this is the normal transmitting and receiving mode of the lin interface, in accordance with lin specification 2.x. the vcc voltage regulator operates with 3. 3v/5v output voltage, with a low toleranc e of 2% and a maximum output current of 85ma. if an undervoltage condition occu rs, nres is switched to low and the ic changes its state to fail-safe mode. 4.2.2 silent mode (sbc only) a falling edge at en while txd is high switches the ic into si lent mode. the txd signal has to be logic high during the mode select window. the transmission path is disabled in silent mode . the voltage regulator is active. the overall supply current from v bat is a combination of the i vssilent = 47a plus the v cc regulator output current i vcc . figure 4-3. switching to silent mode a b active mode vcc: on 5v vcc monitor active unpowered mode all circuitry off a: vs > v vs_th_u_f_up (2.4v) b: vs < v vs_th_u_down (1.9v) delay time silent mode t d _silent = maximum 20s mode select window lin switches directly to recessive mode t d = 3.2s lin vcc nres txd en normal mode silent mode
9 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 in silent mode the internal slave termination between the lin pin and vs pin is disabled to minimize the current consumption in case the pin lin is short-circuited to gnd. only a weak pull-up current (typically 10a) between the lin pin and vs pin is present. silent mode can be activated inde pendently from the current level on pin lin. if an undervoltage condition occurs, nr es is switched to low and the atmel ? sbc changes its state to fail-safe mode. 4.2.3 sleep mode (sbc only) a falling edge at en while txd is low switches the ic into sleep mode. the txd signal has to be logic low during the mode select window ( figure 4-6 ). figure 4-4. switching to sleep mode in order to avoid any influence to the lin pin when switching into sleep mode it is possible to switch the en up to 3.2s earlier to low than the txd. the easiest and best way to do th is is by having two falling edges at txd and en at the same time. in sleep mode the transmission path is disabled. supply current from v bat is typically i vssleep = 9a. the v cc regulator is switched off; nres and rxd are low. the internal slave termi nation between the lin pin and vs pin is disabled to minimize the current consumption in case the lin pin is short-circuited to gnd. only a weak pull-up cu rrent (typically 10a) between the lin pin and the vs pin is present. the sleep mode can be ac tivated independently from the cu rrent level on the lin pin. voltage below the lin pre-wake detection v linl at the lin pin activates the internal lin receiver and starts the wake-up detection timer. if the txd pin is short-circuited to gnd, it is possible to switch to sle ep mode via en after t > t dom . delay time sleep mode t d_sleep = maximum 20s lin switches directly to recessive mode t d = 3.2s lin vcc nres txd en sleep mode normal mode mode select window
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 10 4.2.4 fail-safe mode (sbc only) the device automatically switches to fail-safe mode at syst em power-up. the voltage regulator is switched on. the nres output remains low for t res = 4ms and causes the microcontroller to be rese ted. lin communication is switched off. the ic stays in this mode until en is switched to high. the ic then changes to normal mode. a low at nres switches the ic into fail- safe mode directly. during fail-safe mode the txd pin is an ou tput and, together with the rxd output pin, signals the fail- safe source. if the device enters fail-safe mode coming from the normal mode (en=1) due to an v s undervoltage condition (v s < v vs_th_n_f_down ), it is possible to switch into sleep or silent mode by a falling edge at the en input. with this feature the current consumption can be further reduced. a wake-up event from eit her silent or sleep mode is signalled to the mi crocontroller using the rxd pin and the txd pin. a v s undervoltage condition is also signalled at these two pins. the coding is shown in the table below. a wake-up event switches the ic to fail-safe mode. 4.2.5 active mode (voltage regulator only) the device automatically switches to active mode at system power-up. th e vcc voltage regu lator operates wi th 5v output voltage, with a low tolerance of 2% and a maximum outp ut current of 85ma. the nres output remains low for t res =4ms and causes the microcontroller to be reseted. the current consumption is typically 47a. if an undervoltage condition o ccurs, nres switches to low. table 4-2. signaling in fail-safe mode fail-safe sources txd rxd lin wake-up (lin pin) low low vs th (battery) undervoltage detection (vs < 3.9v) high low
11 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 4.3 wake-up scenarios from silent mode or sleep mode 4.3.1 remote wake-up via lin bus 4.3.1.1 remote wake-up from silent mode (sbc only) a remote wake-up from silent mode is only possible if txd is high. a voltage less than the lin pre-wake detection vlinl at the lin pin activates the internal lin receiver and starts the wake-up detection timer. a falling edge at the lin pin followed by a dominant bus level maintained for a certain period of time (> t bus ) and the following rising edge at pin lin (see figure 4- 5 ) result in a remote wake-up request. the device switches fr om silent mode to fail-safe mode, the vcc voltage regulator remains activated and the internal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at the rxd pin and txd pin (str ong pull-down at txd). en high can be used to switch directly to normal mode. figure 4-5. lin wake-up from silent mode undervoltage detection active silent mode 3.3v/5v fail-safe mode 3.3v/5v normal mode low fail-safe mode normal mode en high high nres en vcc rxd lin bus bus wake-up filtering time t bus high txd high low (strong pull-down)
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 12 4.3.1.2 remote wake-up from sleep mode (sbc only) a falling edge at the lin pin followed by a dominant bus level maintained for a certain period of time (> t bus ) and a following rising edge at the lin pin result in a remote wake-up reques t, causing the device to switch from sleep mode to fail-safe mode. the v cc regulator is activated, and the inter nal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at rxd an d txd (strong pull-down at txd) (see figure 4-6 ). en high can be used to switch directly from sleep/silent mode to fail-safe mode. if en is still high after vcc ramp-up and undervoltage reset time, the ic switches to normal mode. figure 4-6. lin wake-up from sleep mode 4.3.2 wake-up source recognition (sbc only) the device can distinguish between different wake-up sources. the wake-up source can be read on the txd and rxd pin in fail-safe mode. these flags are i mmediately reset if the microcontro ller sets the en pin to high and the ic is in normal mode. t vcc off state on state low fail-safe mode normal mode en high microcontroller start-up time delay reset time low low nres en vcc rxd lin bus bus wake-up filtering time t bus high txd low (strong pull-down) high high table 4-3. signaling in fail-safe mode fail-safe sources txd rxd lin wake-up (lin pin) low low vs th (battery) undervoltage detection (vs < 3.9v) high low
13 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 4.4 behavior under low supply voltage condition after the battery voltage has been connected to the application circuit, the voltage at the vs pin increases according to the block capacitor used in the application (see figure 8-1 on page 23 ). if v vs is higher than the minimum vs operation threshold v vs_th_u_f_up , the ic mode changes from unpowered mode to fail-safe mode. as soon as v vs exceeds the undervoltage threshold v vs_th_f_n_up , the lin transceiver can be activated. the vcc output voltage reaches its nominal value after t vcc . this parameter depends on the externally applied vcc capacitor and the load. the nres output is low for the reset time delay t reset . no mode change is possible during this time t reset . the behavior of vcc, nres and vs is shown in the following diagrams (ramp-up and ramp-down): figure 4-7. vcc and nres versus vs (ramp-up) for 3.3v (sbc only) figure 4-8. vcc and nres versus vs (ramp-down) for 3.3v (sbc only) v (v) vs (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 vs vcc nres v (v) vs (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 vs vcc nres
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 14 figure 4-9. vcc and nres versus vs (ramp-up) for 5v (sbc and voltage regulator) figure 4-10. vcc and nres versus vs (ramp-down) for 5v (sbc and voltage regulator) please note that the upper graphs are only valid if the vs ramp-up and ramp-down times ar e much slower than the vcc ramp-up time t vcc and the nres delay time t reset . if during sleep mode the voltage level of v vs drops below the undervoltage detection threshold v vs_th_n_f_down (typ. 4.3v), the operation mode is not changed and no wake-up is possible. only if the supply voltage on pin vs drops below the vs operation threshold v vs_th_u_down (typ. 2.05v), does the ic switch to unpowered mode. if during silent mode the vcc voltage drops below the vcc undervoltage threshold v vcc_th_uv_down the ic switches into fail- safe mode. if the supply voltage on pin vs drops below the vs operation threshold v vs_th_u_down (typ. 2.05v), does the ic switch to unpowered mode. if during normal mode the voltage level on the vs pin drops belo w the vs undervoltage detection threshold v vs_th_n_f_down (typ. 4.3v), the ic switches to fail-safe mode. this means the lin transceiver is disabled in order to avoid malfunctions or false bus messages. the voltage regulator remains active. for 3.3v sbc : in this undervoltage situation it is possible to swit ch the device into sleep mode or silent mode by a falling edge at the en input. for this feature, switching into these two current saving modes is always guaranteed, allowing current consumption to be reduced even further. when the vcc voltage drops below the vcc undervoltage threshold v vcc_th_uv_down (typ. 2.6v) the ic switches into fail-safe mode. for 5v sbc : because of the vcc undervoltage condition in this situation, the ic is in fail-safe mode and can be switched into sleep mode only. only when the supply voltage v vs drops below the operation threshold v vs_th_u_down (typ. 2.05v) does the ic switch into unpowered mode. the current consumption of the sbc in silent mode or in fa il-safe mode and the voltage regulator is always below 170a, even when the supply voltage vs is lower than the regulator?s nomina l output voltage vcc. v (v) vs (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 vs nres vcc v (v) vs (v) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 vs nres vcc
15 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 4.5 voltage regulator figure 4-11. voltage regulator: supply voltage ramp-up and ramp-down the voltage regulator needs an external capacitor for compensation and to smooth t he disturbances from the microcontroller. it is recommended to use a mlc capacitor with a minimum capacitance of 1.8f together with a 100nf ceramic capacitor. depending on the application, the values of these capacitors can be modified by the customer. during a short circuit at vcc, the output limits the output current to i vcclim . because of undervoltage, nres switches to low and sends a reset to the microcontroller. if the chip temperature exceeds the value t vccoff , the vcc output switches off. the chip cools down and, a fter a hysteresis of t hys , switches the output on again. when the atmel ata6632xx is being soldered onto the pcb it is mandatory to conne ct the heat slug with a wide gnd plate on the printed board to get a good heat sink. the main power dissipation of the ic is created from the vc c output current ivcc, which is needed for the application. ?power dissipation: safe operati ng area: regulator?s output current ivcc versus supply voltage v s ? is shown in figure 4- 12 . figure 4-12. power dissipation: safe operating area: regulator?s output current ivcc versus supply voltage v s at different ambient temperatures (r thja = 50k/w assumed) vs v 12v 5.0v/3.3v 4.8v/2.9v 5.0v/3.3v t vcc t vcc t reset 2.4v t res_f nres t v vs_th_n_f_down v s [v] i_vcc [ma] tamb = 125c tamb = 115c tamb = 105c tamb = 95c tamb = 85c 0 10 20 30 40 50 60 70 80 90 5 6 7 8 9 1011121314 15161718
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 16 5. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. typ. max. unit supply voltage v s v s ?0.3 +40 v pulse time 500ms t a =25c output current i vcc 85ma v s +43.5 v pulse time 2min t a =25c output current i vcc 85ma v s 28 v logic pins voltage levels (rxd, txd, en, nres) v logic ?0.3 +5.5 v logic pins output dc currents i logic ?5 +5 ma lin - dc voltage - pulse time < 500ms v lin ?27 +40 +43.5 v v v cc - dc voltage - dc input current v vcc i vcc ?0.3 +5.5 +200 v ma esd according to ibee lin emc test specification 1.0 following iec 61000-4-2 - pin vs, lin to gnd (w ith external circuitry acc. applications diagram) 6 kv esd hbm following stm5.1 with 1.5k /100pf - pin vs, lin to gnd 6 kv hbm esd ansi/esd-stm5.1 jesd22-a114 aec-q100 (002) 3 kv cdm esd stm 5.3.1 750 v machine model esd aec-q100-revf(003) 200 v junction temperature t j ?40 +150 c storage temperature t s ?55 +150 c
17 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 6. thermal characteristics parameters symbol min. typ. max. unit thermal resistance junction to heat slug r thjc 10 k/w thermal resistance junction to ambient, where heat slug is soldered to pcb according to jedec r thja 50 k/w thermal shutdown of v cc regulator t vccoff 150 165 180 c thermal shutdown of lin output t linoff 150 165 180 c thermal shutdown hysteresis t hys 10 c 7. electrical characteristics 5v < v s < 28v, ?40c < t j < 150c; unless otherwise specifi ed all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* 1 vs pin 1.1 nominal dc voltage range vs v s 5 13.5 28 v a 1.2 supply current in sleep mode sleep mode v lin > v s ? 0.5v v s < 14v, t = 27c vs i vssleep 6 9 12 a b sleep mode v lin > v s ? 0.5v v s < 14v vs i vssleep 3 10 15 a a sleep mode, v lin = 0v bus shorted to gnd v s < 14v vs i vssleep_short 20 50 100 a a 1.3 supply current in silent mode (sbc) / active mode (voltage regulator) bus recessive 5.5v< v s < 14v without load at vcc t=27c vs i vssilent 30 47 58 a b bus recessive 5.5v< v s < 14v without load at vcc vs i vssilent 30 50 64 a a bus recessive 2.0v< v s < 5,5v without load at vcc vs i vssilent 50 130 170 a a silent mode 5.5v< v s < 14v bus shorted to gnd without load at vcc vs i vssilent_short 50 80 120 a a 1.4 supply current in normal mode bus recessive v s < 14v without load at vcc vs i vsrec 150 230 290 a a 1.5 supply current in normal mode bus dominant (internal lin pull-up resistor active) v s < 14v without load at vcc vs i vsdom 200 700 950 a a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 18 1.6 supply current in fail-safe mode bus recessive 5.5v < v s < 14v without load at vcc vs i vsfail 40 55 80 a a bus recessive 2.0v < v s < 5.5v without load at vcc vs i vsfail 50 130 170 a a 1.7 vs undervoltage threshold (switching from normal to fail-safe mode) decreasing supply voltage vs v vs_th_n_f_down 3.9 4.3 4.7 v a increasing supply voltage vs v vs_th_f_n_up 4.1 4.6 4.9 v a 1.8 vs undervoltage hysteresis vs v vs_hys_f_n 0.1 0.25 0.4 v a 1.9 vs operation threshold (switching to unpowered mode) switch to unpowered mode vs v vs_th_u_down 1.9 2.05 2.3 v a switch from unpowered to fail-safe mode vs v vs_th_u_f_up 2.0 2.25 2.4 v a 1.10 vs undervoltage hysteresis vs v vs_hys_u 0.1 0.2 0.3 v a 2 rxd output pin (only sbc) 2.1 low-level output sink capability normal mode, v lin =0v, i rxd =2ma rxd v rxdl 0.2 0.4 v a 2.2 high-level output source capability normal mode v lin =v s , i rxd =?2ma rxd v rxdh v cc ? 0.4v v cc ? 0.2v v a 3 txd input/output pin (only sbc) 3.1 low-level voltage input txd v txdl ?0.3 +0.8 v a 3.2 high-level voltage input txd v txdh 2 v cc + 0.3v v a 3.3 pull-up resistor v txd =0v txd r txd 40 70 100 k a 3.4 high-level leakage current v txd =v cc txd i txd ?3 +3 a a 3.7 low-level output sink current at lin wake-up request fail-safe mode v lin = v s v txd = 0.4v txd i txd 2 2.5 8 ma a 4 en input pin (only sbc) 4.1 low-level voltage input en v enl ?0.3 +0.8 v a 4.2 high-level voltage input en v enh 2 v cc + 0.3v v a 4.3 pull-down resistor v en = vcc en r en 50 125 200 k a 4.4 low-level input current v en = 0v en i en ?3 +3 a a 5 nres open drain output pin 5.1 low-level output voltage v s 5.5v i nres =2ma nres v nresl 0.2 0.4 v a 5.2 undervoltage reset time v vs 5.5v c nres =20pf nres t reset 2 4 6 ms a 5.3 reset debounce time for falling edge v vs 5.5v c nres =20pf nres t res_f 0.5 10 s a 5.4 switch off leakage current v nres =5.5v nres i nres_l ?3 +3 a a 7. electrical charact eristics (continued) 5v < v s < 28v, ?40c < t j < 150c; unless otherwise specifi ed all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
19 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 8 vcc voltage regulator (3.3v) 8.1 output voltage vcc 4v < v s < 18v (0ma to 50ma) vcc vcc nor 3.234 3.366 v a 4.5v < v s < 18v (0ma to 85ma) vcc vcc nor 3.234 3.366 v c 8.2 output voltage v cc at low v s 3v < vs < 4v vcc vcc low v vs ? v d 3.366 v a 8.3 regulator drop voltage vs > 3v, i vcc = ?15ma vcc v d1 100 150 mv a 8.4 regulator drop voltage vs > 3v, i vcc = ?50ma vcc v d2 300 500 mv a 8.5 line regulation maximum 4v < vs < 18v vcc vcc line 0.1 0.2 % a 8.6 load regulation maximum 5ma < i vcc < 50ma vcc vcc load 0.1 0.5 % a 8.7 output current limitation vs > 4v vcc i vcclim ?180 ?120 ma a 8.8 load capacity mlc capacitor vcc c load 1.8 2.2 f d 8.9 vcc undervoltage threshold (nres on) referred to vcc vs > 4v vcc v vcc_th_uv_down 2.3 2.5 2.8 v a vcc undervoltage threshold (nres off) referred to vcc vs > 4v vcc v vcc_th_uv_up 2.5 2.6 2.9 v a 8.10 hysteresis of vcc undervoltage threshold referred to vcc vs > 4v vcc v vcc_hys_uv 100 200 300 mv a 8.11 ramp-up time vs > 4v to vcc = 3.3v c vcc = 2.2f i load = ?5ma at vcc vcc t vcc 1 1.5 ms a 9 vcc voltage regulator (5v) 9.1 output voltage vcc 5.5v < v s < 18v (0ma to 50ma) vcc vcc nor 4.9 5.1 v a 6v < v s < 18v (0ma to 85ma) vcc vcc nor 4.9 5.1 v c 9.2 output voltage v cc at low v s 4v < vs < 5.5v vcc vcc low v vs ? v d 5.1 v a 9.3 regulator drop voltage vs > 4v, i vcc = ?20ma vcc v d1 100 200 mv a 9.4 regulator drop voltage vs > 4v, i vcc = ?50ma vcc v d2 300 500 mv a 9.5 regulator drop voltage vs > 3.3v, i vcc = ?15ma vcc v d3 150 mv a 9.6 line regulation maximum 5.5v < vs < 18v vcc vcc line 0.1 0.2 % a 9.7 load regulation maximum 5ma < i vcc < 50ma vcc vcc load 0.1 0.5 % a 9.8 output current limitation vs > 5.5v vcc i vcclim ?180 ?120 ma a 9.9 load capacity mlc capacitor vcc c load 1.8 2.2 f d 9.10 vcc undervoltage threshold (nres on) referred to vcc vs > 4v vcc v vcc_th_uv_down 4.2 4.4 4.6 v a vcc undervoltage threshold (nres off) referred to vcc vs > 4v vcc v vcc_hys_uv 4.3 4.6 4.8 v a 9.11 hysteresis of undervoltage threshold referred to vcc vs > 5.5v vcc v vcc_hys_uv 100 200 300 mv a 9.12 ramp-up time vs > 5.5v to vcc = 5v c vcc = 2.2f i load = ?5ma at vcc vcc t vcc 1 1.5 ms a 7. electrical charact eristics (continued) 5v < v s < 28v, ?40c < t j < 150c; unless otherwise specifi ed all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 20 10 lin bus driver (only sbc): bus load conditions: load 1 (small): 1nf, 1k ; load 2 (large): 10nf, 500 ; c rxd = 20pf, load 3 (medium): 6.8nf, 660 characterized on samples 12.7 and 12.8 specifies the timing parameters for pr oper operation at 20kb/s a nd 12.9 and 12.10 at 10.4kb/s 10.1 driver recessive output voltage load1/load2 lin v busrec 0.9 v s v s v a 10.2 driver dominant voltage v vs = 7v r load = 500 lin v _losup 1.2 v a 10.3 driver dominant voltage v vs = 18v r load = 500 lin v _hisup 2 v a 10.4 driver dominant voltage v vs = 7v r load = 1000 lin v _losup_1k 0.6 v a 10.5 driver dominant voltage v vs = 18v r load = 1000 lin v _hisup_1k 0.8 v a 10.6 pull-up resistor to v s the serial diode is mandatory lin r lin 20 30 47 k a 10.7 voltage drop at the serial diodes in pull-up path with r slave i serdiode = 10ma lin v serdiode 0.4 1.0 v d 10.8 lin current limitation v bus = v bat_max lin i bus_lim 40 120 200 ma a 10.9 input leakage current at the receiver including pull- up resistor as specified input leakage current driver off v bus = 0v v bat = 12v lin i bus_pas_dom ?1 ?0.35 ma a 10.10 leakage current lin recessive driver off 8v < v bat < 18v 8v < v bus < 18v v bus v bat lin i bus_pas_rec 10 20 a a 10.11 leakage current when control unit disconnected from ground. loss of local ground must not affect communication in the residual network gnd device = v s v bat = 12v 0v < v bus < 18v lin i bus_no_gnd ?10 +0.5 +10 a a 10.12 leakage current at disconnected battery. node has to sustain the current that can flow under this condition. bus must remain operational under this condition. v bat disconnected v sup_device = gnd 0v < v bus < 18v lin i bus_no_bat 0.1 2 a a 10.13 capacitance on pin lin to gnd lin c lin 20 pf d 7. electrical charact eristics (continued) 5v < v s < 28v, ?40c < t j < 150c; unless otherwise specifi ed all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
21 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 11 lin bus receiver (only sbc) 11.1 center of receiver threshold v bus_cnt = (v th_dom + v th_rec )/2 lin v bus_cnt 0.475 v s 0.5 v s 0.525 v s v a 11.2 receiver dominant state v en = 5v/3.3v lin v busdom ?27 0.4 v s v a 11.3 receiver recessive state v en = 5v/3.3v lin v busrec 0.6 v s 40 v a 11.4 receiver input hysteresis v hys = v th_rec ? v th_dom lin v bushys 0.028 v s 0.1 x v s 0.175 v s v a 11.5 pre-wake detection lin high-level input voltage lin v linh v s ? 2v v s + 0.3v v a 11.6 pre-wake detection lin low-level input voltage activates the lin receiver lin v linl ?27 v s ? 3.3v v a 12 internal timers (only sbc) 12.1 dominant time for wake-up via lin bus v lin = 0v lin t bus 50 100 150 s a 12.2 time delay for mode change from fail-safe into normal mode via en pin v en = 5v/3.3v en t norm 5 15 20 s a 12.3 time delay for mode change from normal mode to sleep mode via en pin v en = 0v en t sleep 5 15 20 s a 12.5 txd dominant time-out time v txd = 0v txd t dom 20 40 60 ms a 12.6 time delay for mode change from silent mode into normal mode via en pin v en = 5v/3.3v en t s_n 5 15 40 s a 12.7 duty cycle 1 th rec(max) = 0.744 v s th dom(max) = 0.581 v s v s = 7.0v to 18v t bit = 50s d1 = t bus_rec(min) /(2 t bit ) lin d1 0.396 a 12.8 duty cycle 2 th rec(min) = 0.422 v s th dom(min) = 0.284 v s v s = 7.6v to 18v t bit = 50s d2 = t bus_rec(max) /(2 t bit ) lin d2 0.581 a 12.9 duty cycle 3 th rec(max) = 0.778 v s th dom(max) = 0.616 v s v s = 7.0v to 18v t bit = 96s d3 = t bus_rec(min) /(2 t bit ) lin d3 0.417 a 12.10 duty cycle 4 th rec(min) = 0.389 v s th dom(min) = 0.251 v s v s = 7.6v to 18v t bit = 96s d4 = t bus_rec(max) /(2 t bit ) lin d4 0.590 a 7. electrical charact eristics (continued) 5v < v s < 28v, ?40c < t j < 150c; unless otherwise specifi ed all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 22 figure 7-1. definition of bus timing characteristics 12.11 slope time falling and rising edge at lin v s = 7.0v to 18v lin t slope_fall t slope_rise 3.5 22.5 s a 13 receiver electrical ac parameters of the lin physical layer lin receiver, rxd load conditions: c rxd = 20pf 13.1 propagation delay of receiver v s = 7.0v to 18v t rx_pd = max(t rx_pdr , t rx_pdf ) rxd t rx_pd 6 s a 13.2 symmetry of receiver propagation delay rising edge minus falling edge v s = 7.0v to 18v t rx_sym = t rx_pdr ? t rx_pdf rxd t rx_sym ?2 +2 s a 7. electrical charact eristics (continued) 5v < v s < 28v, ?40c < t j < 150c; unless otherwise specifi ed all values refer to gnd pins. no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit
23 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 8. application circuits figure 8-1. typical application circuit sbc note: heat slug must always be connected to gnd. figure 8-2. typical application circuit voltage regulator note: heat slug must always be connected to gnd. atmel ata663254 ata663231 dfn8 3 x 3 rxd en nres txd vcc vcc microcontroller vcc vbat master node pull up vs lin gnd 100nf c2 220pf 10f/50v c3 c1 d1 2.2f c4 100nf c5 lin gnd gnd r1 10k d2 r2 1k + atmel ata663203 dfn8 3 x 3 nres vcc vcc microcontroller vcc vbat vs gnd 100nf c2 10f/50v c1 d1 2.2f c4 100nf c5 gnd gnd r1 10k +
ata663203/ata663231/ata663254 [datasheet] 9337d?auto?07/14 24 10. package information 9. ordering information extended type number package remarks ata663231-faqw dfn8 3.3v lin system basis chip, pb-free, 6k, taped and reeled ata663254-faqw dfn8 5v lin system basis chip, pb -free, 6k, taped and reeled ata663203-faqw dfn8 5v voltage regulator, pb-free, 6k, taped and reeled package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5165.03-4 1 10/11/13 package: vdfn_3x3_8l exposed pad 2.4x1.6 common dimensions (unit of measure = mm) min nom note max symbol dimensions in mm specifications according to din technical drawings 0.035 0.05 0 a1 33.1 2.9 e 0.3 0.35 0.25 b 0.65 e 0.4 0.45 0.35 l 1.6 1.7 1.5 e2 2.4 2.5 2.3 d2 33.1 2.9 d 0.21 0.26 0.16 a3 0.85 0.9 0.8 a d 1 8 pin 1 id partially plated surface e a a3 a1 b l z 10:1 top view side view bottom view e d2 14 85 e2 z
25 ata663203/ata663231/ ata663254 [datasheet] 9337d?auto?07/14 11. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 9337d-auto-07/14 ? figure 1- 2 ata663203 ?block diagram voltage regulator? on page 3 added ? ata663203 pin configuration on page 4 added ? figure 4-3 ata663203 ?voltage regulator operating modes? on page 8 added ? section 4.2.5 ata663203 ?active mode (voltage regulator only)? on page 10 added ? figure 8-2 ata663203 ?typical application circuit voltage regulator? on page 23 added ? section 9 ata663203 ?ordering information? on page 24 updated
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